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general description the max5134?ax5137 is a family of pin-compatibleand software-compatible 16-bit and 12-bit dacs. the max5134/max5135 are low-power, quad 16-/12-bit, buffered voltage-output, high-linearity dacs. the max5136/max5137 are low-power, dual 16-/12-bit, buffered voltage-output, high-linearity dacs. they use a precision internal reference or a precision external ref-erence for rail-to-rail operation. the max5134?ax5137 accept a wide +2.7v to +5.25v supply-voltage range to accommodate most low-power and low-voltage applica- tions. these devices accept a 3-wire spi-/qspi tm -/ microwire -/dsp-compatible serial interface to save board space and reduce the complexity of optically iso-lated and transformer-isolated applications. the digital interface? double-buffered hardware and software ldac provide simultaneous output updates. the serial interface features a ready output for easy daisy-chain- ing of several max5134?ax5137 devices and/or othercompatible devices. the max5134?ax5137 include a hardware input to reset the dac outputs to zero or mid- scale upon power-up or reset, providing additional safety for applications that drive valves or other transducers that need to be off during power-up. the high linearity of the dacs makes these devices ideal for precision con- trol and instrumentation applications. the max5134 max5137 are available in an ultra-small (4mm x 4mm), 24-pin tqfn package or a 16-pin tssop package. both packages are specified over the -40? to +105? extended industrial temperature range. applications automatic test equipmentautomatic tuning communication systems data acquisition gain and offset adjustment portable instrumentation power-amplifier control process control and servo loops programmable voltage and current sources features ? 16-/12-bit resolution available in a 4mm x 4mm,24-pin tqfn package or 16-pin tssop ? hardware-selectable to zero/midscale dacoutput on power-up or reset ? double-buffered input registers ? ldac asynchronously updates dac outputs simultaneously ? ready facilitates daisy chaining ? high-performance 10ppm/? internal reference ? guaranteed monotonic over all operatingconditions ? wide +2.7v to +5.25v supply range ? rail-to-rail buffered output operation ? low gain error (less than ?.5%fs) and offset(less than ?0mv) ? 30mhz 3-wire spi-/qspi-/microwire-/ dsp-compatible serial interface ? cmos-compatible inputs with hysteresis ? low-power consumption (i shdn = 2 a max) pin-/software-compatible, 16-/12-bit, voltage-output dacs max5134?ax5137 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrated? website at www.maximintegrated.com. evaluation kit available 19-4209; rev 4; 11/13 qspi is a trademark of motorola inc. microwire is a registered trademark of national semiconductor corp. ordering information + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. note: all devices are specified over the -40? to +105? oper- ating temperature range. part pin- package resolution (bits) inl (lsb) max5134 agtg+ 24 tqfn-ep* 16 quad ? MAX5134AGUE+ 16 tssop 16 quad ? max5135 gtg+ 24 tqfn-ep* 12 quad ? max5135gue+ 16 tssop 12 quad ? max5136 agtg+ 24 tqfn-ep* 16 dual ? max5136ague+ 16 tssop 16 dual ? max5137 gtg+ 24 tqfn-ep* 12 dual ? max5137gue+ 16 tssop 12 dual ? functional diagrams, pin configurations, and typical operating circuit appear at end of data sheet. downloaded from: http:///
pin-/software-compatible, 16-/12-bit, voltage-output dacs 2 maxim integrated max5134?ax5137 absolute maximum ratings electrical characteristics (v avdd = 2.7v to 5.25v, v dvdd = 2.7v to 5.25v, v avdd v dvdd , v gnd = 0v, v refi = v avdd - 0.25v, c out = 200pf, r out = 10k , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. avdd to gnd...........................................................-0.3v to +6v dvdd to gnd...........................................................-0.3v to +6v out0?ut3 to gnd ....................................-0.3v to the lower of (avdd + 0.3v) and +6v refi, refo, m/ z to gnd .............................-0.3v to the lower of (avdd + 0.3v) and +6v sclk, din, cs to gnd ................................-0.3v to the lower of (dvdd + 0.3v) and +6v ldac , ready to gnd .................................-0.3v to the lower of (dvdd + 0.3v) and +6v continuous power dissipation (t a = +70?) 24-pin tqfn (derate at 27.8mw/? above +70?)....2222.2mw 16-pin tssop (derate at 11.1mw/? above +70?)....888.9mw maximum current into any input or output with the exception of m/ z pin .......................................?0ma maximum current into m/ z pin ...........................................?ma operating temperature range .........................-40? to +105? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units static accuracy (notes 1, 2) max5134/max5136 16 resolution n max5135/max5137 12 bits (note 3) -8 2 +10 integral nonlinearity (max5134/max5136) inl v refi = 5v, v avdd = 5.25v t a = +25c 6 lsb integral nonlinearity (max5135/max5137) inl v refi = 5v, v avdd = 5.25v -1 +0.25 +1 lsb differential nonlinearity dnl guaranteed monotonic -1.0 +1.0 lsb offset error oe (note 4) -10 1 +10 mv offset-error drift 4 v/c gain error ge (n ote 4) -0.5 0.2 +0.5 % of fs gain temperature coefficient 2 ppm fs/c reference input v avdd = 3v to 5.25v 2 v avdd reference-input voltage range v refi v avdd = 2.7v to 3v 2 v avdd - 0.2 v reference-input impedance 113 k note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . package thermal characteristics (note 1) tqfn junction-to-ambient thermal resistance ( ja ) ............36?/w junction-to-case thermal resistance ( jc ) ...................3?/w tssop junction-to-ambient thermal resistance ( ja ) ............90?/w junction-to-case thermal resistance ( jc ) .................27?/w downloaded from: http:///
pin-/software-compatible, 16-/12-bit, voltage-output dacs maxim integrated 3 max5134?ax5137 parameter symbol conditions min typ max units internal reference reference voltage v refo t a = +25c 2.437 2.440 2.443 v reference temperature coefficient (note 5) 10 25 ppm/c reference output impedance 1 line regulation 100 ppm/v maximum capacitive load c r 0.1 nf dac output voltage (note 2) output voltage range no load 0.02 v avdd - 0.02 v dc output impedance 0.1 series resistance = 0 0.2 nf maximum capacitive load (note 5) c l series resistance = 500 15 f resistive load r l 2 k v avdd = 5.25v 35 short-circuit current i sc v avdd = 2.7v -40 20 +40 ma power-up time from power-down mode 25 s digital inputs (sclk, din, cs , ldac ) (note 6) input high voltage v ih 0.7 x v dvdd v input low voltage v il 0.3 x v dvdd v input leakage current i in v in = 0 or v dvdd -1 0.1 +1 a input capacitance c in 10 pf digital outputs ( ready ) output high voltage v oh i source = 3ma v dvdd - 0.5 v output low voltage v ol i sink = 2ma 0.4 v dynamic performance voltage-output slew rate sr positive and negative 1.25 v/s voltage-output settling time t s 1/4 scale to 3/4 scale v refi = v avdd = 5v settle to 2 lsb (note 5) 5 s digital feedthrough code 0, all digital inputs from 0 to v dvdd 0.5 nv?s major code transition analog glitch impulse 25 nv?s output noise 10khz 120 nv/ h integrated output noise 1hz to 10khz 18 v dac-to-dac crosstalk 25 nv?s electrical characteristics (continued)(v avdd = 2.7v to 5.25v, v dvdd = 2.7v to 5.25v, v avdd v dvdd , v gnd = 0v, v refi = v avdd - 0.25v, c out = 200pf, r out = 10k , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) downloaded from: http:///
pin-/software-compatible, 16-/12-bit, voltage-output dacs 4 maxim integrated max5134?ax5137 electrical characteristics (continued)(v avdd = 2.7v to 5.25v, v dvdd = 2.7v to 5.25v, v avdd v dvdd , v gnd = 0v, v refi = v avdd - 0.25v, c out = 200pf, r out = 10k , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units power requirements (note 7) analog supply voltage range v avdd 2.7 5.25 v digital supply voltage range v dvdd 2.7 v avdd v i avdd 2.5 3.6 ma supply current (max5134/max5135) i dvdd no load, all digital inputs at 0 or dvdd 1 10 a i avdd 1.5 2.3 ma supply current (max5136/max5137) i dvdd no load, all digital inputs at 0 or dvdd 1 10 a i avpd 0.2 2 power-down supply current i dvpd no load, all digital inputs at 0 or dvdd 0.1 2 a timing characteristics (note 8) (figre 1) serial-clock frequency f sclk 0 30 mhz sclk pulse-width high t ch 13 ns sclk pulse-width low t cl 13 ns cs fall-to-sclk fall setup time t css 8 ns sclk fall-to cs -rise hold time t csh 5 ns din-to-sclk fall setup time t ds 10 ns din-to-sclk fall hold time t dh 2 ns sclk fall to ready transition t srl (note 9) 30 ns cs pulse-width high t csw 33 ns ldac pulse width t ldacpwl 33 ns note 1: static accuracy tested without load. note 2: linearity is tested within 20mv of gnd and avdd , allowing for gain and offset error. note 3: codes above 2047 are guaranteed to be within ? lsb . note 4: gain and offset tested within 100mv of gnd and avdd . note 5: guaranteed by design. note 6: device draws current in excess of the specified supply current when a digital input is driven with a voltage of vi < v dvdd - 0.6v or vi > 0.5v. at vi = 2.2v with v dvdd = 5.25v, this current can be as high as 2ma. the spi inputs are cmos-input level com- patible. the 30mhz clock frequency cannot be guaranteed for a minimum signal swing. note 7: excess current from avdd is 10ma when powered without dvdd. excess current from dvdd is 1ma when powered withoutavdd. note 8: all timing specifications are with respect to the digital input and output thresholds. note 9: maximum daisy-chain clock frequency is limited to 25mhz. c7 c6 c5 d2 d1 d0 x command executed on 24th falling edge of sclk cs sclk din x = don't care. t ch t cl t css t dh t csh t ds t srl ready x t csw d3 figure 1. serial-interface timing diagram downloaded from: http:///
pin-/software-compatible, 16-/12-bit, voltage-output dacs max5134/max5136 integral nonlinearity vs. digital input code max5134-max5137 toc01 digital input code (lsb) inl (lsb) 0 16384 32768 63 0 -3-6 -9 9 49152 65536 max5134/max5136 integral nonlinearity vs. analog supply voltage max5134-max5137 toc02 avdd ( v ) inl (lsb) 2.7 3.7 4.7 3.2 4.2 5.2 -9 -7 -5 -3 -1 1 3 5 7 9 max5134/max5136 integral nonlinearity vs. temperature max5134-max5137 toc03 temperature ( c) inl (lsb) -40 100 -20 60 80 40 020 -9 -7 -5 -3 -1 1 3 5 7 9 max5134/max5136 differential nonlinearity vs. digital input code max5134-max5137 toc04 digital input code (lsb) dnl (lsb) 0 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 16384 32768 49152 65536 max5134/max5136 differential nonlinearity vs. analog supply voltage max5134-max5137 toc05 avdd ( v ) dnl (lsb) 2.7 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 3.7 4.7 3.2 4.2 5.2 max5134/max5136 differential nonlinearity vs. temperature max5134-max5137 toc06 temperature ( c) dnl (lsb) -40 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -20 0 20 40 60 80 100 max5134/max5136 offset error vs. analog supply voltage max5134-max5137 toc07 avdd ( v ) offset error (mv) 2.7 3.7 4.7 3.2 4.2 5.2 -10 -8 -6 -4 -2 0 2 4 6 8 10 max5135/max5137 differential nonlinearity vs. digital input code max5134-max5137 toc08 digital input code (lsb) dnl (lsb) 0 3072 1024 2048 4096 -0.10 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.10 max5135/max5137 integral nonlinearity vs. digital input code max5134-max5137 toc09 digital input code (lsb) inl (lsb) 0 3072 1024 2048 4096 -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 typical operating characteristics (t a = +25?, unless otherwise noted.) typical operating characteristics (t a = +25?, unless otherwise noted.) maxim integrated 5 max5134?ax5137 downloaded from: http:///
pin-/software-compatible, 16-/12-bit, voltage-output dacs offset error vs. temperature max5134-max5137 toc10 temperature ( c) offset error (mv) -40 20 80 06 0 -20 40 100 -0.6 -0.3-0.5 -0.2-0.4 -0.1 0 v avdd = 2.7v v refi = 2.5v v avdd = 5.25v v refi = 5v gain error vs. analog supply voltage max5134-max5137 toc11 avdd ( v ) gain error (%fs) 2.7 3.7 4.7 3.2 4.2 5.2 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 gain error vs. temperature max5134-max5137 toc12 temperature ( c) gain error (%fs) -40 20 80 06 0 -20 40 100 0.070 0.0800.076 0.0820.078 0.072 0.074 0.084 0.086 v avdd = 2.7v v avdd = 5.25v analog supply current vs. analog supply voltage max5134-max5137 toc13 supply voltage (v) 4.7 4.2 3.7 3.2 1100 1300 1500 1700 1900 2100 2300 2500 900 2.7 5.2 supply current ( a) v out_ = 0 (max5136/max5137) v out_ = v refo (max5136/max5137) v out_ = 0 (max5134/max5135) v out_ = v refo (max5134/max5135) analog supply current vs. temperature max5134-max5137 toc14 temperature ( c) 20 80 60 40 -40 -20 500 1000 1500 2000 2500 3000 0 0 100 supply current ( a) i dvdd i avdd (max5136/max5137) i avdd (max5134/max5135) analog supply current vs. supply voltage (power-down mode) max5134-max5137 toc15 supply voltage (v) supply current ( a) 4.7 4.2 3.7 3.2 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0 2.7 5.2 t a = +25 c t a = -40 c t a = +105 c exiting/entering power-down mode max5134-max5137 toc16 4 s/div ch1ch0 500mv/div500mv/div major code transition max5134-max5137 toc17 1 s/div 10mv/div settling time up max5134-max5137 toc18 400ns/div 500mv/div 6 maxim integrated max5134?ax5137 typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) downloaded from: http:///
pin-/software-compatible, 16-/12-bit, voltage-output dacs settling time down max5134-max5137 toc19 400ns/div 500mv/div crosstalk max5134-max5137 toc20 4 s/div 10mv/div2v/div digital feedthrough max5134-max5137 toc21 40ns/div 5v/div50mv/div sclk v out_ digital supply current vs. digital supply voltage max5134-max5137 toc22 supply voltage (v) supply current (na) 4.7 4.2 3.7 3.2 2.0 2.5 3.00.5 1.0 1.5 3.5 4.0 0 2.7 5.2 v avdd = 5.25v, sclk = 0hz reference voltage vs. supply voltage max5134-max5137 toc23 supply voltage (v) v refo (v) 4.7 4.2 3.7 3.2 2.42 2.44 2.46 2.48 2.502.40 2.7 5.2 t a = -40 c t a = +105 c t a = +25 c reference voltage vs. temperature max5134-max5137 toc24 temperature ( c) v refo (v) 100 80 60 40 20 0 -20 2.4375 2.4380 2.4385 2.4390 2.4395 2.4400 2.44052.4370 -40 digital supply current vs. digital input voltage max5134-max5137 toc25 digital input voltage (v) digital supply current ( a) 5 4 3 2 1 500 1000 1500 2000 2500 3000 0 0 v avdd = v dvdd = 5.25v up down full-scale output vs. temperature max5134-max5137 toc26 temperature ( c) output voltage (v) 100 80 -20 0 20 40 60 2.44 2.45 2.46 2.47 2.48 2.49 2.50 2.512.43 -40 externalreference 2.500v internalreference output voltage vs. output current max5134-max5137 toc27 output current (ma) output voltage (v) 25 20 15 10 5 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.502.00 03 0 v avdd = 3.3v v avdd = 5v maxim integrated 7 max5134?ax5137 typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) downloaded from: http:///
pin-/software-compatible, 16-/12-bit, voltage-output dacs full-scale reference feedthrough max5134-max5137 toc28 500mv/div 500mv/div0v v ref 0v v out v out_ ref zero-scale reference feedthrough max5134-max5137 toc29 20 s/div 10mv/div 500mv/div v out_ v ref reference input response vs. frequency max5134-max5137 toc30 input frequency (khz) attenuation (db) 10,000 1000 100 10 -40 -35 -30 -25 -20 -15 -10 -5 0 5 -45 1 power-up glitch, zero scale, external reference max5134-max5137 toc31 1v/div 2v/div v out_ v avdd power-up glitch, zero scale, internal reference max5134-max5137 toc32 2v/div1v/div v avdd v out_ power-up glitch, midscale, external reference max5134-max5137 toc33 2v/div1v/div v avdd v out_ power-up glitch, midscale, internal reference max5134-max5137 toc34 2v/div1v/div v avdd v out_ dc noise spectrum, fft plot max5134-max5137 toc35 2.5khz/div 25khz -40dbm10db/div 8 maxim integrated max5134?ax5137 typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) downloaded from: http:///
detailed description the max5134?ax5137 is a family of pin-compatibleand software-compatible 16-bit and 12-bit dacs. the max5134/max5135 are low-power, quad 16-/12-bit, buffered voltage-output, high-linearity dacs. the max5136/max5137 are low-power, dual 16-/12-bit, buffered voltage-output, high-linearity dacs. the max5134?ax5137 minimize the digital noise feedthrough from input to output by powering down the sclk and din input buffers after completion of each 24- bit serial input. on power-up, the max5134?ax5137 reset the dac outputs to zero or midscale, depending on the state of the m/ z input, providing additional safety for applications that drive valves or other transducers thatneed to be off on power-up. the max5134?ax5137 contain a segmented resistor string-type dac, a serial-in parallel-out shift register, a dac register, power-on reset (por) circuit, and control logic. on the falling edge ofthe clock (sclk) pulse, the serial input (din) data is shifted into the device, msb first. during power-down, an internal 80k resistor pulls dac outputs to gnd. output amplifiers (out0?ut3) the max5134?ax5137 include internal buffers for alldac outputs. the internal buffers provide improved load regulation and transition glitch suppression for the dac outputs. the output buffers slew at 1.25v/? and drive up to 2k in parallel with 200pf. the analog supply voltage (avdd) determines the maximum output voltage rangeof the device as avdd powers the output buffers. dac reference internal reference the max5134?ax5137 feature an internal referencewith a nominal output of +2.44v. connect refo to refi pin-/software-compatible, 16-/12-bit, voltage-output dacs maxim integrated 9 max5134?ax5137 pin description pin max5134 max5135 max5136 max5137 tqfn-ep tssop tqfn-ep tssop name function 1 3 1 3 out0 channel 0 buffered dac output 2, 5, 8, 11, 14, 17, 20, 23 2, 5, 6, 8, 11, 13, 14, 17, 20, 23 6, 11 n.c. no connection. not internally connected. 3 4 3 4 dvdd digital power supply. bypass dvdd with a 0.1f capacitor to gnd. 4 5 4 5 ready active-low ready. indicated configuration ready. use ready as cs for consecutive part or as feedback to the c. 6 6 out3 channel 3 buffered dac output 7, 19 7, 15 7, 19 7, 15 gnd ground 9 8 9 8 din data in 10 9 10 9 cs active-low chip-select input 12 10 12 10 sclk serial-clock input 13 11 out2 channel 2 buffered dac output 15 12 15 12 ldac load dac input. active-low hardware load dac input. 16 13 16 13 m/ z power-up reset select. connect m/ z to v avdd to power up the dac outputs to midscale. connect m/ z to gnd to power up the dac outputs to zero. 18 14 18 14 out1 channel 1 buffered dac output 21 16 21 16 refo reference voltage output 22 1 22 1 refi reference voltage input. bypass refi with a 0.1f capacitor to gnd when using external reference. 24 2 24 2 avdd analog power supply. bypass avdd with a 0.1f capacitor to gnd. ep exposed pad. not internally connected. connect to a ground or leave unconnected. not intended as an electrical connection point. downloaded from: http:///
when using the internal reference. bypass refo tognd with a 47pf (maximum 100pf) capacitor. alternatively, if heavier decoupling is required, use a 1k resistor in series with a 1? capacitor in parallel with the existing 100pf capacitor. refo can deliver upto 100? of current with no degradation in perfor- mance. configure other reference voltages by applying a resistive potential divider with a total resistance greater than 33k from refo to gnd. external reference the external reference input features a typical inputimpedance of 113k and accepts an input voltage from +2v to avdd. connect an external voltagesupply between refi and gnd to apply an ex- ternal reference. leave refo unconnected. visit www.maximintegrated.com/products/references for a list of available external voltage-reference devices. avdd as reference connect avdd to refi to use avdd as the reference voltage. leave refo unconnected. serial interface the max5134?ax5137 3-wire serial interface is com-patible with microwire, spi, qspi, and dsps (figures 2, 3). the interface provides three inputs, sclk, cs , and din and one output, ready . use ready to verify communication or to daisy-chain multiple devices (seethe ready section). ready is capable of driving a 20pf load with a 30ns (max) delay from the falling edgeof sclk. the chip-select input ( cs ) frames the serial data loading at din. following a chip-select input?high-to-low transition, the data is shifted synchronously and latched into the input register on each falling edge of the serial-clock input (sclk). each serial word is 24 bits. the first 8 bits are the control word followed by 16 data bits (msb first), as shown in table 1. the serial input register transfers its contents to the input registers after loading 24 bits of data. to initiate a new data transfer, drive cs high, keep cs high for a minimum of 33ns before the next write sequence. the sclk can beeither high or low between cs write pulses. figure 1 shows the timing diagram for the complete 3-wire serial-interface transmission. pin-/software-compatible, 16-/12-bit, voltage-output dacs 10 maxim integrated max5134?ax5137 24-bit word control bits data bits msb lsb c7 c6 c5 c4 c3 c2 c1 c0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6?0 desc function 0 0 0 0 0 0 0 0 x x x x x x x x x x nop no operation. 0 0 0 0 0 0 0 1 xxxx dac 3 dac 2 dac 1 dac 0 x x ldac move contents of inputto dac registers indicated by 1?. no effect on registers indicated by 0?. 0 0 0 0 0 0 1 0 x x x x x x x x x x clr software clear. 0 0 0 0 0 0 1 1 xxxx dac 3 dac 2 dac 1 dac 0 ready_en x power control power down dacs indicated by 1?. set ready_en = 1 to enable ready . 0 0 0 0 0 1 0 1 0 0 0 0 0 0 lin 0 0 0 linearity optimize dac linearity. 0 0 0 1 dac 3 dac 2 dac 1 dac 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 write write to selected inputregisters (dac output not affected). 0 0 1 1 dac 3 dac 2 dac 1 dac 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 write- through write to selected inputand dac registers, dac outputs updated (writethrough). 0 0 1 0 0 0 0 0 x x x x x x x x x x nop no operation. table 1. operating mode truth table** for the max5136/max5137, dac2 and dac3 do not exist. for the max5135/max5137, d0?3 are don?-care bits. downloaded from: http:///
pin-/software-compatible, 16-/12-bit, voltage-output dacs maxim integrated 11 max5134?ax5137 sclk din ready* cs si*i/o so sk microwire port *the ready-to-si connection is not required for writing to the devices * but may be used for transmission verification. max5134 max5137 figure 2. connections for microwire the max5134?ax5137 digital inputs are doublebuffered. depending on the command issued through the serial interface, the input register(s) can be loaded without affecting the dac register(s) using the write command. to update the dac registers, either pulse the ldac input low to synchronously update all dac outputs, or use the soft-ware ldac command. use the writethrough commands (see table 1) to update the dac outputs immediately afterthe data is received. only use the writethrough command to update the dac output immediately. the max5134/max5136 dac code is unipolar binary with v out_ = (code/65,536) x v ref . the max5135/ max5137 dac code is unipolar binary with v out_ = (code/4096) x v ref . see table 1 for the serial interface commands.connect the max5134?ax5137 dvdd supply to the supply of the host dsp or microprocessor. the avdd supply may be set to any voltage within the operating range of 2.7v to 5.25v, but must be greater than orequal to the dvdd supply. writing to the devices write to the max5134?ax5137 using the followingsequence: 1) drive cs low, enabling the shift register. 2) clock 24 bits of data into din (c7 first and d0 last), observing the specified setup and hold times. bitsd15?0 are the data bits that are written to the internal register. 3) after clocking in the last data bit, drive cs high. cs must remain high for 33ns before the next transmis-sion is started. figure 1 shows a write operation for the transmission of24 bits. if cs is driven high at any point prior to receiving 24 bits, the transmission is discarded. ready* din sclk cs sck ss i/o mosi +5v miso* spi/qspi port *the ready-to-miso connection is not required for writing to the devices but may be used for transmission verification. max5134 max5137 figure 3. connections for spi/qspi cs din sclk ready 1ready 3 ready 2 12 3 2 4 22 21 20 4 3 2 1 23 24 22 21 5 4 3 2 1 23 24 22 21 5 4 3 2 slave 1 data slave 2 data slave 3 data figure 4. ready timing downloaded from: http:///
ready connect ready to a microcontroller (?) input to moni- tor the serial interface for valid communications. theready pulse appears 24 clock cycles after the nega- tive edge of cs (figure 4). since the max5134 max5137 look at the first 24 bits of the transmission fol-lowing the falling edge of cs , it is possible to daisy chain devices with different command word lengths.ready goes high 16ns after cs is driven high. daisy chain multiple max5134?ax5137 devices byconnecting the first device conventionally, then connect its ready output to the cs of the following device. repeat for any other devices in the chain, and drive thesclk and din lines in parallel (figure 5). when sending commands to daisy-chained devices, the devices are accessed serially starting with the first device in the chain. the first 24 data bits are read by the first device, the second 24 data bits are read by the second device and so on (figure 4). figure 6 shows the configuration when cs is not driven by the ?. these devices can be daisy chained with other compatible devices such as themax15500 output conditioner. to perform a daisy-chain write operation, drive cs low and output the data serially to din. the propagation ofthe ready signal then controls how the data is read by each device. as the data propagates through the daisychain, each individual command in the chain is execut- ed on the 24th falling clock edge following the falling edge of the respective cs input. to update just one device in a daisy chain, send the no-op command tothe other devices in the chain. if ready is not required, write command 0x03 (power control) and set ready_en = 0 (see table 1) to dis-able the ready output. clear command the max5134?ax5137 feature a software clear com-mand (0x02). the software clear command acts as a software por, erasing the contents of all registers. all outputs return to the state determined by the m/ z input. power-down mode the max5134?ax5137 feature a software-controlled individual power-down mode for each channel. theinternal reference and biasing circuits power down to conserve power when all 4 channels are powered down. in power-down, the outputs disconnect from the buffers and are grounded with an internal 80k resis- tor. the dac register holds the retained code so thatthe output is restored when the channel powers up. the serial interface remains active in power-down mode. load dac ( ldac ) input the max5134?ax5137 feature an active-low ldac logic input that allows the outputs to update asynchro-nously. keep ldac high during normal operation (when the device is controlled only through the serialinterface). drive ldac low to simultaneously update all dac outputs with data from their respective input regis-ters. figure 7 shows the ldac timing with respect to out_. holding ldac low causes the input registers to become transparent and data written to the dac regis-ters to immediately update the dac outputs. a software command can also activate the ldac operation. to activate ldac by software, set control word 0x01 and data bits a11?8 to select which dac to load, and allother data bits to don? care. see table 1 for the data format. this operation updates only the dac outputs that are flagged with a 1. dac outputs flagged with a 0 remain unchanged. pin-/software-compatible, 16-/12-bit, voltage-output dacs 12 maxim integrated max5134?ax5137 c slave 1 sclk dincs ready mosi i/o sck slave 3 sclk dincs ready slave 2 sclk dincs ready max5134max5137 max5134max5137 max5134max5137 figure 5. daisy-chain configuration downloaded from: http:///
pin-/software-compatible, 16-/12-bit, voltage-output dacs maxim integrated 13 max5134?ax5137 cs dwrite sclk dread cssclk din slave 1 slave 2 slave n error int c cs1 csm to other chips/chains ready dout cssclk din ready cssclk din ready max5134max5137 max5134 max5137 max15500 figure 6. daisy chain ( cs not used) downloaded from: http:///
applications information power-on reset (por) on power-up, the input registers are set to zero, dacoutputs power up to zero or midscale, depending on the configuration of m/ z . connect m/ z to gnd to power the outputs to gnd. connect m/ z to avdd to power the outputs to midscale.to guarantee dac linearity, wait until the supplies have settled. set the lin bit in the dac linearity register; wait 10ms, and clear the lin bit. unipolar output the max5134?ax5137 unipolar output voltage rangeis 0 to v refi . the output buffers each drive a load of 2k in parallel with 200pf. bipolar output use the max5134?ax5137 in bipolar applications with additional external components (see the typical operating circuit ). power supplies and bypassing considerations for best performance, use a separate supply for themax5134?ax5137. bypass both dvdd and avdd with high-quality ceramic capacitors to a low-imped- ance ground as close as possible to the device. minimize lead lengths to reduce lead inductance. connect both max5134?ax5137 gnd inputs to the analog ground plane. layout considerations digital and ac transient signals on gnd inputs can cre-ate noise at the outputs. connect both gnd inputs to form the star ground for the dac system. refer remote dac loads to this system ground for the best possible performance. use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return paths back to the max5134?ax5137 gnd. carefully lay out the traces between channels to reduce ac crosscoupling and crosstalk. do not use wire-wrapped boards and sockets. use shielding to improve noise immunity. do not run analog and digital signals parallel to one anoth- er (especially clock signals) and avoid routing digital lines underneath the max5134?ax5137 package. definitions integral nonlinearity (inl) inl is the deviation of the measured transfer functionfrom a best fit straight line drawn between two codes. for the max5134/max5136, this best fit line is a line drawn between codes 3072 and 64,512 of the transfer function, once offset and gain errors have been nullified. for the max5135/max5137, this best fit line is a line drawn between codes 192 and 4032 of the transfer func- tion, once offset and gain errors have been nullified. differential nonlinearity (dnl) dnl is the difference between an actual step heightand the ideal value of 1 lsb. if the magnitude of the dnl is greater than -1 lsb, the dac guarantees no missing codes and is monotonic. pin-/software-compatible, 16-/12-bit, voltage-output dacs 14 maxim integrated max5134?ax5137 dac latch contents msb lsb analog output, v out_ 1111 1111 1111 1111 v ref x (65,535/65,536) 1000 0000 0000 0000 v ref x (32,768/65,536) = 1/2 v ref 0000 0000 0000 0001 v ref x (1/65,536) 0000 0000 0000 0000 0 ldac out_ ? lsb t s t ldacpwl figure 7. output timing table 2. max5134/max5136 input codevs. output voltage dac latch contents msb lsb analog output, v out_ 1111 1111 1111 xxxx v ref x (4095/4096) 1000 0000 0000 xxxx v ref x (2048/4096) 0000 0000 0001 xxxx v ref x (1/4096) 0000 0000 0000 xxxx 0 table 3. max5135/max5137 input codevs. output voltage downloaded from: http:///
offset error offset error indicates how well the actual transfer func-tion matches the ideal transfer function at a single point. typically, the point at which the offset error is specified is at or near the zero-scale point of the transfer function. gain error gain error is the difference between the ideal and theactual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. settling time the settling time is the amount of time required from thestart of a transition, until the dac output settles to the new output value within the converter? specified accuracy. digital feedthrough digital feedthrough is the amount of noise that appearson the dac output when the dac digital control lines are toggled. digital-to-analog glitch impulse a major carry transition occurs at the midscale pointwhere the msb changes from low to high and all other bits change from high to low, or where the msb changes from high to low and all other bits change from low to high. the duration of the magnitude of the switching glitch during a major carry transition is referred to as the digital-to-analog glitch impulse. digital-to-analog power-up glitch impulse the digital-to-analog power-up glitch is the duration ofthe magnitude of the switching glitch that occurs as the device exits power-down mode. dc dac-to-dac crosstalk crosstalk is the amount of noise that appears on a dacoutput set to 0 when the other dac is updated from 0 to avdd chip information process: bicmos pin-/software-compatible, 16-/12-bit, voltage-output dacs maxim integrated 15 max5134?ax5137 pin configurations 2324 22 21 87 9 n.c. ready n.c. out3** 10 out0 n.c.ldac n.c. out1out2** 12 refi 456 17 18 16 14 13 n.c. avdd csdin *exposed pad. **n.c. for the max5136/max5137. *ep n.c.gnd max5134? max5137 dvdd m/z 3 15 ref0 20 11 n.c. n.c. 19 12 sclk gnd + top view 1615 14 13 12 11 10 1 23 45 6 7 refognd out1 m/z dvdd out0 avdd refi max5134? max5137 ldac out2** sclk gnd out3 9 8c s din ready tssop + downloaded from: http:///
pin-/software-compatible, 16-/12-bit, voltage-output dacs 16 maxim integrated max5134?ax5137 input register input register input register input register 12-/16-bit dac 12-/16-bit dac 12-/16-bit dac 12-/16-bit dac bufferbuffer buffer buffer control logic por power-down control serial-to- parallel converter cs sclk din out0 refi reference avdd dvdd out1 ldac out2 out3 ready refo gnd m/z max5134 max5135 dac register dac register dac register dac register functional diagrams downloaded from: http:///
pin-/software-compatible, 16-/12-bit, voltage-output dacs maxim integrated 17 max5134?ax5137 input register input register 12-/16-bit dac 12-/16-bit dac bufferbuffer control logic por power-down control serial-to- parallel converter cs sclk din out0 refi reference avdd dvdd ldac out1 ready refo gnd m/z max5136max5137 dac register dac register functional diagrams (continued) downloaded from: http:///
pin-/software-compatible, 16-/12-bit, voltage-output dacs 18 maxim integrated max5134?ax5137 dac cssclk din r1 r2 dvdd avdd out refo gnd 100nf m/zldac digital power supply analog power supply 100nf ready refi 47pf 100nf note: shown in bipolar configuration. max5134?max5137 typical operating circuit package information for the latest package outline information and land patterns ( footprints), go to www.maximintegrated.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but th e drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 24 tqfn-ep t2444+4 21-0139 90-0022 16 tssop u16+2 21-0066 90-0117 downloaded from: http:///
pin-/software-compatible, 16-/12-bit, voltage-output dacs max5134?ax5137 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 19 2013 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/08 initial release of max5134. 1 10/08 initial release of max5135/max5136/max5137. 1?9 added the tssop package to the ordering information table, absolute maximum ratings section, and pin description table. 1, 2, 9 changed the major code transition analog glitch impulse parameter in the electrical characteristics table from 12nv ? s (typ) to 25nv ? s (typ). 3 in the typical operating characteristics ; added ?clk = 0hz?to toc22, changed toc28 to ?00mv/div?from ?00mv? and changed the title of toc30 to ?eference inputresponse vs. frequency. 7, 8 added a statement to the internal reference section regarding using a resistor in series. 10 changed the functional diagrams to show ldac drawn to the dac register. 16, 17 2 1/10 replaced the typical operating circuit to show the correct op amp. 18 3 1/13 revised the absolute maximum ratings and added the package thermal characteristics section. updated the electrical characteristics table. 2?, 9 4 11/13 revised ordering information .1 downloaded from: http:///

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